The Rise of Superconducting Erasure Qubits – an Industry Perspective

TECHNICAL BLOG The Rise of Superconducting Erasure Qubits – an Industry Perspective Building a commercially useful quantum computer requires more than increasing qubit numbers. The real challenge is reducing errors to the point where quantum processors can reliably outperform classical systems on meaningful problems. Maria Violaris DEVELOPER ADVOCATE Maria has a hybrid role at OQC of quantum error correction research towards building a fault-tolerant quantum computer, and technical science communication. She has a PhD in theoretical quantum information from the University of Oxford, alongside which she interned with IBM Quantum making the “Quantum Paradoxes” YouTube series. She has spearheaded multiple new initiatives in the quantum community, including the “Quantum on the Clock” Schools Video Competition; Oxford Quantum Information Society; and quantum computing workshops. She has also written for Physics World magazine; published quantum education research; and hosts a Quantum Foundations Podcast on her YouTube channel, amongst other quantum content. Today’s superconducting qubits have made remarkable progress, but error rates remain too high for large-scale, fault-tolerant quantum computing. That’s why quantum error correction (QEC) is one of the defining engineering challenges for the industry. At OQC, we are taking a hardware-first approach to solving it. Our latest Perspective article, Developments in superconducting erasure-qubits for hardware-efficient quantum error correction, explores one of the most promising directions in the field: superconducting erasure qubits. It also explains how our newly developed OQC Dimon architecture fits within the rapidly evolving research landscape. Engineering qubits that reveal their own errors Traditional quantum error correction assumes errors occur silently, requiring significant overhead to detect and correct them. Erasure qubits however, change that assumption. An erasure error occurs when a qubit leaves its computational states, |0⟩ or |1⟩, and moves into a detectable state outside the computational space. Crucially, this tells us both where and when an error has occurred, without disturbing the ongoing computation.This additional information makes quantum error correction dramatically more efficient. Erasure-based architectures therefore offer two significant advantages: Higher error thresholds. Because error locations are known, error-correcting codes can tolerate substantially more physical noise before failing, bringing fault tolerance closer to the capabilities of near-term superconducting hardware. Smaller logical qubits. Fewer physical qubits are needed to achieve the same logical error rates, reducing hardware requirements and improving scalability. Rather than relying solely on increasingly complex software-based correction, erasure qubits build error correction into the hardware itself. OQC Dimon visualisation Introducing the OQC Dimon At OQC, we’ve redesigned our proprietary Coaxmon qubit into a new multimodal architecture: the OQC Dimon. The Dimon reduces our dominant noise source by 10×, providing a scalable foundation for hardware-efficient quantum error correction. Its key innovation is its minimalist implementation of a dual-rail erasure qubit. By introducing an additional superconducting island within the existing Coaxmon footprint, we’ve transformed a single qubit into a dual-mode system without increasing the overall hardware footprint. In effect, two modes work together as one logical unit, allowing the qubit to identify its own failures while maintaining an efficient physical design. This creates an “inner code” directly within the hardware. Multiple of these protected qubits can then be combined into larger logical qubits using an “outer code”, creating two complementary layers of protection against errors. A growing direction for superconducting quantum computing Dual-rail encoding has become an increasingly active area of research across the superconducting quantum computing community. In this approach, logical states are encoded across two modes: Logical 0 is represented as |01⟩ Logical 1 is represented as |10⟩ The dominant failure mechanism in superconducting systems is relaxation to |00⟩. Rather than treating this simply as another error, dual-rail architectures transform it into a detectable erasure event. Researchers across academia and industry are exploring a variety of physical implementations, including coupled transmons and cavity-QED systems. The OQC Dimon takes a different approach by integrating this capability within the compact Coaxmon architecture, preserving scalability while minimising additional hardware complexity. Looking beyond today’s qubits The Perspective article also examines several broader developments shaping the future of erasure-based quantum computing, including: techniques for engineering hardware with more favourable error behaviour; recent theoretical advances that optimise quantum error correction using erasure information; emerging methods for producing higher-quality magic states, a critical ingredient for universal fault-tolerant quantum computing. Together, these advances point towards a future where quantum hardware is designed with error correction as a core architectural principle, rather than an additional layer applied afterwards. Building fault tolerance into the hardware Quantum error correction will ultimately determine how quickly the industry reaches commercially useful quantum computing. Erasure qubits represent an important shift in thinking: designing hardware that not only performs quantum operations, but actively supports more efficient fault tolerance from the outset. The OQC Dimon is one example of this philosophy in practice, combining hardware efficiency with a scalable path towards logical qubits capable of supporting real-world quantum applications. As the field continues to evolve, purpose-built architectures like these will play an increasingly important role in delivering the next generation of superconducting quantum computers. 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