Researchers Limit Decoder Costs for Faster Fault-Tolerant Computation

Fault-tolerant quantum computation using surface codes previously required syndrome extraction rounds proportional to code distance, denoted as O(d), between logical operations. Shota Ikari from RIKEN and colleagues have created PACE, a decoder-aware scheduling framework for transversal CNOT gates which reduces this requirement to O, accelerating computation for platforms with long-range connectivity. This advancement mitigates increased classical decoding workload through techniques including hybrid window decoding, in-time DEM compilation, and sub-window parallel decoding. PACE is a new framework designed to tackle the substantial computational demands of error correction in functional quantum computers. While advances in quantum gate techniques offer potential for faster calculations, they simultaneously increase the workload for conventional computers verifying the results. PACE optimises this verification process, ensuring that gains in quantum speed are not hampered by limitations in decoding ability. Shota Ikari from RIKEN and colleagues have unveiled PACE, addressing a key bottleneck in quantum computing: increasing demands on classical computers verifying quantum calculations. Improvements in quantum gate technology promise faster processing but also burden systems responsible for checking results for errors. The surface code relies on repeatedly checking relationships between qubits, known as syndrome extraction, to identify and correct errors; this is akin to taking a medical scan without disturbing the patient. However, denser scheduling of operations expands the area needing verification, potentially overwhelming existing capabilities. This expansion arises because each transversal CNOT (TCNOT) gate introduces potential error propagation across multiple physical qubits within the encoded logical qubit. PACE optimises this verification process, mitigating challenges of increased computational load and just-in-time error mapping, detailed prediction of potential errors similar to weather forecasting, ensuring that quantum speed gains are not lost due to decoding limitations. Reduced syndrome extraction accelerates fault-tolerant quantum computation using PACE framework A substantial reduction in the computational demands of fault-tolerant quantum computation has been achieved through collaboration between researchers at institutions including The University of Tokyo and RIKEN. They lowered the number of syndrome extraction rounds required between logical operations from a scaling of O(d) to O, representing a major improvement over previous methods reliant on lattice surgery, a technique involving physically moving qubits around the chip to facilitate gate operations. This breakthrough enables accelerated computation for quantum platforms featuring long-range connectivity, such as those utilising neutral atoms where individual atoms serve as qubits capable of interacting across significant distances, by overcoming a key limitation previously hindering practical application. Neutral atom systems benefit particularly because their inherent connectivity reduces the need for complex qubit routing which adds overhead in traditional surface code implementations. The PACE framework mitigates increased classical decoding workload associated with dense transversal CNOT gate schedules via techniques like hybrid window decoding, just-in-time DEM compilation and sub-window parallel decoding. The core principle involves dividing the quantum chip into smaller ‘windows’ allowing decoders to focus on localised errors before combining results; this is more efficient than attempting to decode the entire system simultaneously.

The team’s DEM Stitch method also accelerated online detector error model (DEM) compilation, which translates physical qubit imperfections into probabilistic models used by the decoder. It proved to be 108.4 times faster than full-circuit Stim construction for a code distance of 23, meeting a 23 millisecond deadline for memory windows and TCNOT windows spanning up to four patches. Stim is a widely used software framework for simulating surface code computations. Reducing the median peak decoding volume by a factor of 3.0 was achieved through enabling Sub-window Parallel Decoding for dense workloads; this technique allows multiple sub-windows within the chip to be decoded concurrently on different classical processing units, though these gains diminish as transversal CNOT gate spacing approaches the code distance. Many scientists aim to build practical quantum computers, but error correction remains a formidable challenge. Quantum information is inherently fragile, susceptible to noise from environmental interactions which introduce errors into calculations. Error correction codes like the surface code protect against these errors by encoding logical qubits, representing actual data, using many physical qubits and employing redundancy to detect and correct faults without destroying the encoded information. Denser schedules of transversal CNOT gates, a method linking quantum bits while preserving their encoded state, place greater demands on classical computers verifying results; however this new PACE framework offers a pathway to mitigate those requirements. Accelerating quantum operations necessitates equally efficient classical verification, which PACE directly addresses by integrating decoding constraints into the scheduling of quantum gates. Transversal CNOT gates and techniques like just-in-time DEM compilation are utilised by PACE to lessen the computational burden of denser gate schedules, thereby reducing the need for repeated error checks. The efficiency gains stem from optimising how TCNOTs are arranged within the surface code layout, minimising long-range dependencies that complicate decoding. Current classical computing power represents a bottleneck for fully realising faster quantum calculations because syndrome extraction and subsequent decoding require significant processing resources; so further work will focus on optimising the balance between quantum speed and classical verification time.

The team is currently investigating extending these techniques to larger circuits alongside exploring alternative decoding algorithms such as belief propagation or machine learning approaches to reduce classical overhead even further. Ultimately, achieving scalable fault-tolerant quantum computation requires co-design of both quantum hardware and its associated classical control infrastructure. The research demonstrated a framework called PACE which manages the increased demands placed on classical computers when using transversal CNOT gates in error correction. This matters because accelerating quantum operations relies not only on improving physical qubits but also on efficiently verifying results with conventional computing resources. PACE achieves this by optimising how gates are scheduled within the surface code layout, reducing the complexity of subsequent data processing. The authors are currently extending these techniques to larger circuits and exploring alternative decoding algorithms to minimise computational overhead further. 👉 More information🗞 Do Not Let CNOTs Overwhelm the Decoder: Scheduling Transversal Gates for Fast FTQC✍️ Shota Ikari, Yuga Hirai, Yasunari Suzuki, Hiroshi Nakamura and Yosuke Ueno🧠 ArXiv: https://arxiv.org/abs/2608.11719 Stay currentSee today’s quantum computing news on Quantum Zeitgeist for the latest breakthroughs in qubits, hardware, algorithms, and industry deals. Tags: