RAQM: Eight qubits stored in a single superconducting memory module

Researchers have now stored eight qubits within a single superconducting memory module, a development addressing a critical gap in quantum processor design. The work, a collaboration spanning SLAC and Fermi National Accelerator Laboratory alongside Stanford, University of Chicago, NYU, and Rutgers, realizes an 8-bit cascaded random access quantum memory. This architecture introduces a key feature absent in current systems: a functional equivalent to classical dynamic random access memory (DRAM), enabling resource-efficient control of qubits and separate optimization of logic and storage.

The team demonstrates arbitrary random access with an average infidelity per mode, characterizing the many-body interactions that contribute to errors. Cascaded RAQM Architecture Enables Scalable Quantum Control A single transmon qubit now addresses eight memory modes within a newly realized superconducting system, a development promising to significantly reduce the control complexity of scaling quantum processors. This cascaded random access quantum memory (RAQM) architecture achieves this by layering a buffer interface between the processor and a multimode storage cavity, effectively multiplexing control resources and isolating storage from processor-induced nonlinearities. The system demonstrates a baseline swap infidelity of < 0.5% when accessing an individual memory mode, a performance level already below practical error-correction thresholds. The RAQM design directly addresses a key limitation in current quantum computing approaches: the linear scaling of control lines with qubit count. By integrating each processor qubit with a memory unit containing multiple storage modes, the architecture expands logical capacity without a corresponding increase in control infrastructure. This approach differs from quantum random access memory (QRAM) because it utilizes classical addressing to transfer logical states between storage and the processor, avoiding the need for coherent quantum addressing schemes. The all-to-all connectivity within the RAQM module also facilitates transversal gates between memory layers, potentially decreasing the time required for multi-logical-qubit operations compared to systems limited by edge-to-edge connectivity. The RAQM’s layered structure is critical to its function; the buffer layer, facing the processor, is engineered for strong coupling and fast control, acting as a temporary staging area for quantum states. Conversely, the storage layer, comprised of weakly coupled quantum memories, prioritizes coherence over gate operations. This separation allows for the optimization of each layer for its specific role, enhancing overall system performance. Characterization of the system revealed that many-body dephasing between storage modes increases with memory size, but is projected to remain small compared to individual mode decoherence for memory sizes ranging from 10 to 100, a scale at which the RAQM can already achieve control-line efficiency. The aggregate error rate for memory sizes up to 7 modes remains below the depolarization threshold (~17%) of the surface code, establishing the RAQM as a viable, scalable unit cell for fault-tolerant superconducting quantum computers. Researchers suggest a more linearized coupler design, incorporating multiple junctions in series, or a balanced design could mitigate these interactions. “This enables the cascaded RAQM structure to serve as a building block for quantum error correction codes, using a single extra control line to enable scaling logical qubits by an amount limited by the coherence and the unwanted interactions among the memories,” the paper states. The implications of this architecture extend beyond hardware efficiency, offering a pathway toward more scalable and manageable quantum systems. By decoupling logic and storage, the RAQM allows for independent optimization of these subsystems, potentially leading to significant improvements in both performance and resource utilization. The ability to perform transversal operations within the memory module further streamlines quantum computations, reducing the overhead associated with complex multi-qubit operations. This design establishes a scalable unit cell for building fault-tolerant quantum architectures, a significant step toward realizing practical quantum computation. Transmon-Cavity Coupling for Eight-Mode Quantum Memory This precise control allows for the transfer of quantum states, initiating a three-step process of read, gate operation, and write to access specific memory modes. The architecture’s performance relies on carefully managing parasitic cross-Kerr interactions, induced by nonlinear control elements, between all modes within the system. Characterizing the memory’s performance involved benchmarking the information transfer process, specifically measuring the error imparted on each mode during a read/write operation on a size-7 RAQM. Results indicate an error rate of approximately 1.2 ms per mode, necessitating periodic refresh using quantum error correction techniques to maintain data integrity. This analysis involved extracting the random read infidelity for varying RAQM sizes, providing important data for optimizing memory performance and reliability. The fidelity of the random read operation is impacted by several error channels, with storage decay and cross-Kerr interactions identified as the dominant contributors. Detailed analysis, presented in Supplementary Section X of the published work, breaks down the error budget, revealing the relative importance of each error source. While bosonic modes within a linear cavity are inherently non-interacting, the introduction of nonlinear control elements inevitably induces these parasitic cross-Kerr interactions. This architecture offers a pathway toward reducing the number of control lines needed per logical qubit, a critical factor in scaling quantum systems. High-Coherence Storage Achieved in 3D Superconducting Cavities The realization of a functional 8-bit random access quantum memory (RAQM) represents a departure from conventional quantum processor design by directly addressing the need for on-chip storage, a capability previously lagging behind processing advancements. This new architecture integrates long-lived storage with non-linear processor qubits, allowing for independent optimization of coherence and gate fidelity, a critical step toward scalable quantum computing. The device, fabricated using 3D superconducting flute cavities, hosts multiple high-coherence bosonic modes within a single physical component, effectively increasing logical capacity without a proportional increase in control complexity. The design tackles a fundamental conflict in quantum hardware; high-fidelity gates demand strong interactions and nonlinearity, while extended storage requires linear, weakly interacting systems. Measurements reveal the highest coherence times within the storage modes exceed 1.2 ms, a value that directly impacts the potential for long-duration quantum computations and reduces intrinsic decoherence errors. The RAQM’s architecture is built upon 3D superconducting flute cavities, engineered to host multiple bosonic modes, and fabricated on a single high-purity aluminum bulk. This approach contrasts with designs relying on niobium cavities, which, while proven to achieve coherence times exceeding 20 milliseconds, offers a compact, on-chip solution. The device comprises two layers: a storage layer and a buffer layer, with the buffer connected to a transmon processor for both readout and gate operations. “Niobium cavities have been proven to have T_1 beyond 20 ms, which will significantly reduce the intrinsic decoherence error of the memories,” the researchers note, highlighting a potential pathway for further performance gains. The implications extend beyond simply increasing storage capacity; the RAQM architecture supports over 100 memory modes, potentially enabling the storage of significantly more logical qubits.

Random Access Demonstrates 0.5% Swap Infidelity Measurements reveal a swap infidelity below 0.5% when accessing individual storage modes within a newly realized random access quantum memory (RAQM), a critical threshold for maintaining quantum information during read and write operations. This level of performance surpasses earlier demonstrations and establishes a path toward scalable on-chip quantum memory, previously a lagging component in quantum processor development. The RAQM architecture achieves this fidelity by carefully isolating memory modes from processor non-linearities using an intermediate buffer layer. This multiplexing significantly expands logical capacity, a key challenge in building larger, more powerful quantum computers. Detailed benchmarking of a seven-mode RAQM shows that each read or write operation imparts an error of approximately 1.2% on each mode, a figure that necessitates periodic quantum error correction to maintain data integrity. Further analysis identified the primary sources of error as coupler heating and cavity dephasing, though the current swap time of 0.5 microseconds is limited by frequency crowding. Importantly, the measured swap infidelity satisfies the stringent one percent threshold typically required for active two-qubit gates within the surface code, a promising architecture for fault-tolerant quantum computing. Because memory access operations occur less frequently than active gates, this performance provides a substantial margin for error correction.

The team also characterized state-dependent access errors, combining swap infidelity with contributions from spectator modes, storage locations not currently being accessed, and identified spectator-access dephasing as a dominant error source during inactive periods. Ramsey experiments revealed an average Ramsey dephasing rate of the storage modes at approximately 17%, slightly higher than the average Ramsey dephasing rate of the storage modes themselves. The researchers found that cross-Kerr interactions between storage modes contribute to many-body dephasing during idle periods, but the overall error budget remains manageable. “Although the spectator-access dephasing error is dominant, it is due to the long inactive access period compared to other stages of RAQM control,” the paper states, highlighting the architecture’s potential for optimization. This detailed characterization of error sources and the demonstration of sub-0.5% swap infidelity represent a step toward building practical, scalable quantum memories capable of supporting complex quantum computations. Many-Body Interactions Characterized in RAQM Module Characterizing interactions between multiple quantum bits within a single module is now possible, as demonstrated by a new random access quantum memory (RAQM) capable of storing eight qubits. This achievement addresses a critical bottleneck in superconducting quantum processor development, where memory capacity has previously lagged behind processing power. Detailed benchmarking of the RAQM module revealed the sources of error beyond simple qubit decay, specifically characterizing additional overhead from decoherence between memory modes.

The team divided the RAQM operation cycle into active access, spectator access, and idle periods to isolate error contributions from each stage. This detailed analysis allowed the creation of an error budget for random read fidelity, identifying storage decay, dephasing, and spectator-access dephasing as the primary error channels. The error rate for memory sizes up to seven modes remains below the depolarization threshold of approximately ~17 percent, a level important for surface code error correction.

The team found that the spectator-access dephasing error, while dominant, stems from the extended inactive access period relative to other control stages. Further improvements, such as linearized coupler designs with multiple junctions or balanced designs, could suppress many-body interactions between buffer and storage modes, enhancing performance still further. Source: https://www.nature.com/articles/s41567-026-03418-w More like thisQuantum Research NewsOrigin Quantum Superconducting processor routes qubits coherentlyTechnologyQuantum Storage: 0.86 Fidelity for Path QubitsQuantum AlgorithmsSuperconducting Qubit & Resonator Run Quantum AlgorithmsTechnology NewsQRAM: Quantum Memory for Faster AlgorithmsStay currentSee today’s quantum computing news on Quantum Zeitgeist for the latest breakthroughs in qubits, hardware, algorithms, and industry deals. Tags: Ivy Delaney Ivy Delaney has been working with neural networks and machine learning since the mid-nineties, back when a couple of hidden layers and a long afternoon of training counted as ambitious. She has watched the field go from academic curiosity to the thing quietly running underneath everything, and she brings that long view to quantum computing.

For Quantum Zeitgeist she covers the ground where the two fields meet. That means quantum machine learning and the variational algorithms it leans on, and it also means the less glamorous but more interesting story of classical machine learning already doing real work inside quantum machines, decoding error-correcting codes, calibrating noisy hardware and learning the error models that simulators depend on. She writes about the hardware those algorithms have to run on too, and about the post-quantum cryptography scramble that the same hardware has set off. Her stories typically start with the paper, whether that is peer-reviewed work, conference proceedings or an arXiv preprint, with the source linked so you can hold a claim up against the research it came from. She is unimpressed by benchmarks that will not say what they beat, and by demonstrations that only work in the press release.