Quandela and NVIDIA Outline Photonic QPU Integration Architecture via NVQLink

Quandela and NVIDIA Outline Photonic QPU Integration Architecture via NVQLink Photonic quantum computing developer Quandela and NVIDIA have published a joint technical white paper outlining an architectural framework to integrate photonic Quantum Processing Units (QPUs) into classical AI and High-Performance Computing (HPC) environments using NVIDIA NVQLink. Presented at IEEE Quantum Week 2026 in Toronto, the paper defines a progressive operational model for co-locating photonic QPUs alongside GPU and CPU supercomputing nodes within data centers. The technical integration links Quandela’s proprietary Quantum System Controller (QSC)—which governs real-time FPGA pulse control and optoelectronic routing for its MosaiQ QPU—directly to NVIDIA GPU nodes using NVQLink’s low-latency interconnect architecture. Built on Remote Direct Memory Access over Converged Ethernet (RoCE) operating at sub-4-microsecond round-trip latency budgets, the setup permits microsecond-scale execution loops between GPU classical nodes and QPU control electronics. This enables GPU-accelerated state-vector and tensor-network dynamics simulations, real-time quantum error correction (QEC) decoding, and automated QPU pulse calibration to execute within a unified host process running NVIDIA CUDA-Q and the open-source MerLin Quantum Machine Learning (QML) framework. [ Quandela & NVIDIA Hybrid Photonic Architecture Parameters ]System LayerHardware & Transport StackSoftware & Algorithmic FrameworkPhotonic QPU Control• Quandela Quantum System Controller (QSC)• FPGA Real-Time Optoelectronic Control• Direct Hardware Driver Execution• Scalable Spin-Optical QPU IntegrationInterconnect Infrastructure• NVIDIA NVQLink (RoCE Transport Protocol)• Sub-4 Microsecond Round-Trip Latency• Microsecond GPU-QSC Real-Time Callbacks• RDMA Low-Latency Network CouplingHybrid Compute Stack• NVIDIA Hopper / Blackwell GPU Nodes• MosaiQ & SPOQC Photonic Hardware• NVIDIA CUDA-Q & cuQuantum SDKs• MerLin Photonic QML Framework & Digital Twins The white paper structures commercial adoption across three phases: Access (cloud-hosted experimentation), Integration & Discovery (on-premises GPU-QPU co-location and application profiling), and Scale (deployment of fault-tolerant SPOQC spin-optical architectures). Under CTPO Jean Senellart and NVIDIA Director of Quantum Product Sam Stanwyck, the demonstrator expands Quandela’s hardware integration roadmap following its June low-latency benchmarks and previous HPC deployment agreements across European supercomputing centers. Review the news release via Quandela Newsroom here, download the joint white paper on Quandela Technical Papers here, and examine our previous analysis of NVIDIA’s NVQLink Integration Across the Quantum Ecosystem here. September 14, 2026 Mohamed Abdel-Kareem2026-09-14T22:32:49-07:00 Leave A Comment Cancel replyComment Type in the text displayed above Δ This site uses Akismet to reduce spam. Learn how your comment data is processed.