Google Quantum AI & DeepMind Demonstrate Modular Hyperbolic Codes for Over 30x QEC Overhead Reduction

Simulation data for modular hyperbolic codes using an SI1000 noise model. In a joint technical manuscript published on arXiv, researchers from Google Quantum AI, Google DeepMind, and MIT have introduced a modular quantum error correction (QEC) architecture that reduces physical qubit overhead by more than 30x compared to standard 2D surface codes. The study (“Low-Overhead Quantum Error Correction with Boundary-Connected Planar Modules“) demonstrates that networking small, flat 2D Euclidean planar chips (~100 qubits) via sparse, static inter-module boundary couplers arranged in a hyperbolic tiling geometry (genus g ≥ 2) unlocks the high encoding rates of Quantum Low-Density Parity-Check (qLDPC) codes without requiring complex on-chip long-range wire crossings. [ Fault-Tolerant Memory Architecture Benchmark Comparison ]QEC Memory ArchitectureCode Parameters [[n, k, d]]Physical Qubits / Logical QubitHardware & Interconnect Complexity• Euclidean Surface Code• [[~20,000, 20, 22]]• > 1,000 physical / logical• Monolithic 2D nearest-neighbor planar grid.• Two-Gross Bivariate Bicycle Code• [[288, 12, 18]]• 48 physical / logical (~20x savings)• Monolithic chip requiring dense, crossing long-range couplers.• Modular Hyperbolic Surface Code• [[6000, 146, 20]]• ~95 physical / logical (10x–15x savings)• Modular 116-qubit planar modules; flexible inter-module edge links.• Modular Hyperbolic Color Code• [[6400, 104, 30]]• 36 physical / logical (> 30x savings)• Modular 72-qubit planar modules; rate k/n = 1/16 at distance d ≥ 22. By fine-graining closed hyperbolic surfaces with Euclidean lattice patches of side-length L, the architecture partitions the global QEC code into flat 72-qubit or 116-qubit modules. Stabilizers spanning adjacent modules are measured across boundary seams using cat-flagged syndrome extraction circuits. Circuit-level simulations under the SI1000 noise model (p = 0.1%) decoded via the AlphaQubit neural network and correlated minimum-weight perfect matching (MWPM) demonstrated high tolerance to elevated inter-module seam noise (p_seam = 1%), maintaining low logical error rates even when inter-chip cable error rates are 10x higher than on-chip gate errors. To support universal fault-tolerant logic without space overhead, the team developed fault-tolerant walking circuits that execute logical gates via code automorphisms (global tiling permutations) alongside modular ribbon extractors—a closed ancilla loop attached along module boundaries that is ~4.5x smaller than the memory itself. Review the technical manuscript on arXiv here. In GQI Portal The players behind the news The team that writes QCR tracks every company, deal and technology in the GQI Factory, GQI's verified database of the quantum industry. Next up: every story linked to its players, coming to QCR's paid plans. Players →Companies and institutions across the quantum industry, by segment. Scorecards →How the players compare on hardware, software, funding and more. Newsletter QCR Alerts in your inbox The latest reporting and analysis from Quantum Computing Report. Free, unsubscribe any time. Sign up for QCR Alerts Leave a commentCancel replyAll fields are required. Your email address will not be published.CommentName Email Type in the text displayed above Δ