University of California Si/SiGe Qubits Hit 5 meV Valley Splitting

Researchers at the University of California and University at Buffalo demonstrated 5 meV valley splitting through simulations of silicon-germanium qubits, a result that surpasses values reported in nearly all previous theoretical studies. This advance addresses a critical challenge in scaling silicon-based quantum computing, where maintaining stable qubit performance has been hampered by the small and inconsistent energy gap known as valley splitting.

The team employed a Si/SiGe heterostructure design, combining a narrow quantum well, a small germanium spike, and a pure-germanium cap, to enhance this crucial property. Device-scale simulations, incorporating the impact of atomic-level imperfections, demonstrated a tight distribution across disorder realizations, suggesting a viable path toward reproducible qubit behavior at scale. Silicon-Germanium Heterostructures for Si Spin Qubits Researchers at the University of California and University at Buffalo have demonstrated this enhanced performance through a novel design that diverges from conventional approaches to silicon spin qubit development. Their work, detailed in recent findings, focuses on manipulating the energy separation of key electron states within the quantum well, a critical factor for reliable qubit operation. This configuration allows for significantly higher valley splitting, the energy difference between the lowest conduction band states, than previously observed in theoretical models. The researchers employed device-scale simulations incorporating atomistic alloy disorder through a 1D tight-binding theory to model the complex interplay of materials at the atomic level. These simulations revealed that the design not only boosts valley splitting but also ensures a tight distribution across disorder realizations, a vital characteristic for building qubits that perform consistently at scale. Achieving valley splittings well in excess of the thermal energy of electrons and avoiding valley excitations is essential for the consistent initialization, operation, and readout of gate-defined Si spin qubits, the authors explain, highlighting the practical implications of their findings. The innovation stems from three key design choices: a narrow quantum well between 2.5 and 3.0 nm, a pure-germanium cap, and a strategically placed dilute germanium spike. The pure-Ge cap is designed to create a sharper interface with the silicon well, maximizing valley splitting. The driving force for Si-Ge interdiffusion at the top of the well is partly set by the energetic preference for Ge-Ge nearest-neighbor bonding, which is suppressed by a pure-Ge cap, the team notes, explaining the thermodynamic basis for this approach. The researchers found that even a small fraction of germanium in the spike, when combined with sharp interfaces, can substantially enhance valley splitting without introducing excessive disorder or spin-orbit coupling. The simulations indicate that maintaining a consistent valley splitting of around 1 meV requires sharpness within experimentally realizable limits, offering a clear path forward for scalable Si/SiGe spin qubit devices. Their work addresses a longstanding challenge in scaling these devices, specifically the sensitivity of valley splitting to alloy disorder within the quantum well structure. This enhancement stems from a departure from conventional Si/SiGe heterostructure designs. This approach, as described in their findings, aims to create sharper interfaces and maximize valley splitting while minimizing the impact of atomic-level imperfections. Researchers at the University of California, Los Angeles and the University at Buffalo demonstrated through simulations that a pure-Ge cap addresses a key issue: the energetic preference for Ge-Ge bonding, which suppresses interdiffusion and maintains interface sharpness. If realized experimentally, these results offer a clear path forward to effectively eliminate valley splitting as a problem for large scale SiGe-based quantum processors. Researchers at the University of California, Los Angeles, and the University at Buffalo demonstrate, through device-scale simulations, that their proposed approach yields large valley splittings with a tight distribution across disorder realizations. The approach rests on a Si/SiGe heterostructure design combining a narrow quantum well, a small Ge spike, and a pure-Ge cap. Further analysis focused on the impact of interface roughness, and the simulations quantified how broadening the interfaces between the pure-Ge cap and Ge spike erodes the achievable valley splitting. They found that maintaining a consistent splitting of around 1 meV requires interface sharpness within experimentally realizable limits. The researchers used parameters including a thin cap, a 2.5-3.0 nm well width, and a dilute Ge spike in their simulations. Researchers are targeting valley splittings exceeding 15 microelectronvolts, as electron thermal energies are approximately 15 μeV, but maintaining this separation and ensuring uniformity across a processor has proven challenging.

The team reports demonstrating a pathway toward this goal through an unconventional approach to heterostructure engineering. They used parameters including the quantum well width (between 2.5 and 3.0 nanometers), a dilute germanium spike, and a thin pure-Ge cap to achieve these results. This sharpness minimizes unwanted alloy disorder, a major source of variability in valley splitting. They acknowledge that silicon quantum wells as thin as 3 nanometers have already been successfully grown, suggesting the feasibility of realizing this design, and they identified specific parameters for the simulations. Conventional approaches to enhancing valley splitting in silicon-germanium heterostructures often fall short of delivering the consistency needed for scalable quantum computing, but a new design strategy centered on interface engineering is demonstrating promising results. While germanium spikes and narrow wells have been explored previously, the incorporation of a pure-Ge cap represents a departure from typical designs employing 30% SiGe caps. Researchers at the University of California, Los Angeles demonstrate through simulations that this pure-Ge layer creates a significantly sharper interface with the silicon well, boosting valley splitting. This sharpness stems from the energetic preference for germanium-germanium bonding, suppressing interdiffusion, a phenomenon observed in earlier studies of Ge wetting layers. This is advantageous because introducing germanium into silicon quantum wells can introduce unwanted disorder and spin-orbit coupling. The researchers report identifying specific parameters used in the simulations, and these findings offer a clear pathway toward scalable Si/SiGe spin qubit devices, potentially resolving a key obstacle to large-scale quantum processors. The researchers found the optimized values for this heterostructure design by using atomically sharp interfaces and varying the pure-Ge cap thickness, well width, and the Ge spike fraction, identifying parameters for use in the simulations. Therefore, it is desirable to find strategies that require as low Ge concentrations as possible, they state. Source: https://arxiv.org/abs/2607.09652 Stay currentSee today’s quantum computing news on Quantum Zeitgeist for the latest breakthroughs in qubits, hardware, algorithms, and industry deals. Tags: