Diraq and imec Demonstrate Eight-Qubit Linear Array Fabricated on 300 mm CMOS Silicon Foundries

Overview of the operation and calibration of an 8-dot device. Quantum engineering pioneer Diraq has announced a validation milestone in silicon-based solid-state quantum architectures with the publication of its peer-reviewed paper, “Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device,” in Nature Communications. In direct collaboration with European nanoelectronics hub imec, the research team successfully scaled a linear array of silicon spin qubits from a two-qubit unit cell to an integrated eight-qubit processor. Crucially, the multi-qubit device was manufactured entirely within a commercial, industry-standard 300 mm Silicon Metal-Oxide-Semiconductor (SiMOS) foundry line, demonstrating that highly uniform, qubit-grade quantum dot configurations can be replicated at volume without sacrificing fundamental quantum coherence or gate operational control. [ Diraq - imec 8-Qubit Hardware Matrix ] Fabrication Node ──► imec 300 mm industrial SiMOS production line on isotopically purified 28Si. Array Configuration ──► 8-dot linear chain managed as 4 double quantum dot (DQD) unit cells. Dephasing Time (T2*)──► Ramsey dephasing intervals reaching up to 41 µs (Average ~21 µs). Coherence (T2 Hahn) ──► Hahn-echo coherence times reaching up to 1.31 ms (Average ~0.7 ms). Readout Architecture──► Two-step cascaded charge-sensing to minimize wire count and thermal load. The Architecture of the 8-Dot SiMOS Micro-Array The physical device utilizes electron spins confined within electrostatically defined quantum dots as effective spin-half systems. The layer stack is fabricated on an epitaxially grown silicon substrate isotopically purified to a residual 29Si concentration of only 400 ppm to eliminate ambient nuclear spin dephasing. A triple-layer overlapping polycrystalline silicon gate stack—patterned with a tight 90 nm gate pitch—is used to outline the quantum dots instead of traditional aluminum gates, significantly reducing low-temperature lattice strain at the vital Si/SiO2​ interface. To simplify calibration and tuning, the 8-dot linear array is divided into four modular unit cells of two qubits per double quantum dot (DQD), positioned underneath independent plunger (Pi​) and barrier (Ji​) electrodes. Single-electron transistors (SETs) are micro-fabricated exclusively at the lateral ends of the chain, leaving the inner cores clear of heavy wiring. Individual qubit addressability is maintained via small variations in the electron g-factors across a distribution of Δg=2.17×10−3. This spatial variation allows a global, homogeneous out-of-plane magnetic field (B1​) driven by an integrated titanium nitride (TiN) microwave stripline antenna to trigger target single-qubit quantum gates (Xπ/2​) via precise, resonant electron spin resonance (ESR) frequencies around 14 GHz inside an in-plane static DC Zeeman field of B0​=0.5 T.

Cascaded Readout Mechanics and Performance Integrity A primary engineering triumph of the 8-qubit expansion is the successful verification of a cascaded charge-sensing protocol to measure the central four qubits (P3​ through P6​). Rather than running additional lithographed readout lines that would increase the device’s physical footprint and thermal load inside the dilution refrigerator, the central pairs leverage Pauli spin blockade (PSB) to trigger an electron cascade through the adjacent lateral sub-systems. When a targeted spin pair transitions, it prompts a localized, sequential charge movement across neighboring dots, shifting the electrostatics of the terminal edge dots. These shifts are immediately captured by the terminal SETs with a high signal-to-noise ratio (SNR), validating a highly compact readout architecture that scales efficiently without requiring an unsustainable increase in control lines. Extending the array from two to eight physical quantum dots yielded no systemic degradation in core performance metrics, resolving a long-standing concern regarding device variability across foundry-scaled lines. The processed qubits demonstrated remarkable coherence values: Ramsey Dephasing Times (T2*) : Clocked up to 41±2 μs across the array (with a stable ensemble average of 21±9 μs). Hahn-Echo Coherence Times (T2​Hahn): Reached up to 1.31±0.04 ms (maintaining an average of 0.7±0.4 ms), matching or exceeding values from delicate academic cleanrooms. Furthermore, the team validated coherent nearest-neighbor coupling by demonstrating controlled exchange operations (CZ gates) via square baseband voltage pulses across barrier gate J1​, mapping an exponential turn-on parameter of 33.69±0.01 dec/V. Diraq’s Commercial Horizon Led by Founder and CEO Andrew Dzurak, Diraq is leveraging this multi-qubit milestone to anchor its commercial product timeline. Because the footprint of a SiMOS quantum dot is roughly the same size as a standard classical transistor, millions of qubits can theoretically fit onto a single, compact silicon chip. This dense scaling property allows Diraq to bypass the massive physical infrastructure footprints required by superconducting loops or trapped-ion vacuum chambers. The company’s active roadmap aims to scale these linear configurations into two-dimensional arrays, moving toward hundreds of qubits in the near term, with a long-term strategy to deliver thousands of qubits by 2029 and over one million qubits by 2031. The official corporate milestone disclosures, technical timing data, and forward-looking system integration roadmaps can be reviewed here. The underlying physical proofs, multi-qubit operational datasets, and complete open-access academic manuscript can be reviewed directly within the Nature Communications here. July 9, 2026