Bypassed IBM's Level 3 compiler via JIT hardware routing. Achieved a 170% signal retention boost on a 5-Qubit Asymmetrical EfficientSU2 circuit (ibm_fez)

A researcher bypassed IBM’s Level 3 quantum compiler using just-in-time (JIT) hardware routing on the ibm_fez processor, demonstrating a novel optimization technique for near-term quantum devices. The experiment focused on a 5-qubit Asymmetrical EfficientSU2 circuit, a benchmark for evaluating gate efficiency and error mitigation in superconducting quantum hardware. Signal retention improved by 170% compared to IBM’s default compilation pipeline, suggesting JIT routing may significantly reduce decoherence and operational errors in noisy intermediate-scale quantum (NISQ) systems. Tests were conducted in May 2026 on IBM’s ibm_fez processor, a 7-qubit Falcon-class device, highlighting real-world performance gains achievable through low-level hardware interventions. This work underscores the potential of dynamic routing strategies to outperform static compiler optimizations, offering a path to better circuit execution in current quantum architectures.