IQM Quantum Computers Minimizes Qubit Footprint via Planar Directional Tile Codes

IQM Quantum Computers Minimizes Qubit Footprint via Planar Directional Tile Codes Superconducting hardware developer IQM Quantum Computers has introduced a quantum error correction (QEC) architecture termed directional tile codes. Co-authored with academic teams at Freie Universität Berlin, the University of Edinburgh, and Johannes Gutenberg-Universität Mainz, the research outlines a framework to implement high-rate Quantum Low-Density Parity-Check (qLDPC) codes on standard, two-dimensional planar processor layouts. By validating these error-correcting codes on a strictly planar grid, the approach reduces the physical physical-to-logical qubit overhead up to 1,000 times compared to traditional surface codes, bypassing the need for long-range couplers, three-dimensional vertical routing lines, or complex physical mechanical qubit shuttling mechanisms.

Spacetime Routing Arrays and Mobile Check Paths Traditional high-efficiency qLDPC code variants generally demand complex, non-local check-data connectivity grids that are structurally impossible to map statically within a flat, two-dimensional coordinate system without routing line overlaps. IQM’s approach resolves this structural constraint by compiling the required stabilizer interactions into a dynamic, time-ordered sequence called a directional word. During a syndrome extraction round, check qubits do not remain stationary; instead, they move through a sequence of nearest-neighbor directions—North, East, South, and West—across the hardware grid. Whenever these traveling check qubits pass an active data qubit or a dedicated routing site, they execute localized exchange sequences to continuously extract and process error data. This mobile routing setup is driven by the native exchange mechanics of the iSWAP and CXSWAP two-qubit gate configurations already operational across IQM’s Crystal processor family. Instead of relying on static, long-range physical wires etched onto the silicon chip, the system uses the iSWAP gate’s intrinsic swap behavior as a dual entangling and space-routing mechanism. The quantum state information moves dynamically through the plane during the gate execution sequence itself. This configuration enables the hardware to measure complex, high-efficiency error-correcting codes while preserving a uniform, constant-depth syndrome extraction cycle that remains independent of the total code block scale. Leakage Suppression and Hardware Footprint Compilations Beyond minimizing physical qubit counts, the dynamic circuit architecture addresses leakage noise—a common operational error source in superconducting systems where physical qubits drift out of their defined computational state boundaries into higher energy levels. Because the dynamic syndrome extraction routing paths naturally swap the physical roles of the data and check qubits at the completion of each verification loop, both qubit sets undergo an automated reset sequence every other round. This iterative erasure path flushes out accumulated out-of-bounds energy states, preventing leakage states from propagating across the processor grid and stabilizing long-duration fault-tolerant memories. To evaluate circuit-level performance, the research consortium simulated the footprint of a large-scale memory array encoding 140 logical qubits. The results show that directional tile codes, such as the compact [[323, 14, 15]] code variant, achieve an order-of-magnitude increase in code-efficiency ratios relative to standard rotated surface-code memories. When compiled under a realistic physical error rate of $0.001$, the directional tile-code configurations protect information at a hardware footprint of roughly 30 total circuit qubits per logical qubit. This layout maintains a per-logical per-round error suppression rate up to three orders of magnitude lower than surface codes of equivalent block capacities, establishing a hardware blueprint for upcoming utility-scale processors. The comprehensive technical findings, hardware parameters, and cross-institution error-correction data can be reviewed in the full scientific paper available on arXiv here, with corporate roadmap timelines and commercial listing milestones accessible through the IQM Press Center here. June 23, 2026 Mohamed Abdel-Kareem2026-06-23T08:33:35-07:00 Leave A Comment Cancel replyComment Type in the text displayed above Δ This site uses Akismet to reduce spam. Learn how your comment data is processed.