UCSB & Tohoku University Detail Digital Design for Scalable P-bit Computing
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Researchers at the University of California, Santa Barbara and Tohoku University, in collaboration with the Taiwan Semiconductor Manufacturing Company (TSMC), have developed a fully digital design for scalable probabilistic computing components, known as p-bits. This innovation removes the need for bulky, power-hungry digital-to-analog converters (DACs) traditionally required to control p-bit output, utilizing instead stochastic magnetic tunnel junctions and digital circuits for signal timing. This approach enables the creation of p-bits capable of efficiently exploring multiple possibilities—a key advancement for solving complex optimization and inference tasks currently challenging for traditional computers. Fully Digital p-bit Design Eliminates DACs A new design from researchers at UC Santa Barbara and Tohoku University eliminates the need for digital-to-analog converters (DACs) in probabilistic bit (p-bit) design. Traditional p-bits relied on these analog components to control the likelihood of a 0 or 1 output, creating limitations in scalability due to their size, power consumption, and cost. This breakthrough uses stochastic magnetic tunnel junctions (MTJs) and digital circuits to adjust p-bit behavior, offering a fully digital approach to probabilistic computing. This DAC-free p-bit design utilizes small electronic devices – MTJs – which naturally fluctuate between states. By feeding this random bitstream into a digital circuit with controlled timing, the output probability can be tuned. Importantly, this system compensates for variations between individual devices, enhancing robustness during manufacturing. The researchers demonstrated this compensation, achieving uniform input-output characteristics in their tests with stochastic magnetic tunnel junctions. The new design addresses key obstacles in hardware-based probabilistic computing, enabling self-organization and “on-chip annealing.” The system updates its internal state independently, allowing parallel processing without a central controller. Furthermore, by adjusting timing settings, the system can gradually refine solutions, a method demonstrated by successfully solving a three-dimensional spin-glass problem with 512 spins. This advancement promises more efficient probabilistic computing for applications like artificial intelligence and logistics. Tuning p-bit Behavior with Digital Circuits Researchers have developed a new fully digital p-bit design that eliminates the need for bulky, power-hungry digital-to-analog converters (DACs) traditionally used to control the 0/1 output probability. This breakthrough uses stochastic magnetic tunnel junctions (MTJs) – devices that randomly switch between states – and a digital circuit to tune p-bit behavior via controlled timing of signals. The resulting design promises to enable scalable probabilistic computing hardware, overcoming limitations of previous analog-reliant approaches. This new approach achieves two key capabilities. First, the system self-organizes, allowing many p-bits to operate in parallel without a central controller. Second, it enables “on-chip annealing” – a method of refining solutions – by adjusting timing settings instead of rewriting parameters.
Results demonstrate successful computation of optimal combinations in a three-dimensional spin-glass problem (8x8x8 = 512 spins) using this method, illustrating the system’s computational potential. The digital p-bit design is compatible with modern semiconductor manufacturing, requiring less area and power than existing technologies. Importantly, the digital circuitry compensates for variations in the MTJs themselves, ensuring robustness despite manufacturing differences. This advancement paves the way for practical probabilistic computing applications in fields like artificial intelligence, logistics, and scientific discovery, as presented at IEDM 2025 on December 10, 2025. This remarkable new design developed by the research team requires far less area and power than alternatives, while also being compatible with modern semiconductor manufacturing. On-Chip Annealing and Self-Organization Capabilities This new p-bit design achieves both self-organization and on-chip annealing capabilities. The system updates its internal state in a self-organizing manner, allowing multiple p-bits to operate in parallel without a central controller. Additionally, on-chip annealing is enabled by adjusting basic timing settings within the circuit, rather than rewriting stored parameters, allowing the system to gradually narrow down solutions to complex problems. Researchers demonstrated this annealing process by solving a three-dimensional spin-glass problem with 512 spins. By gradually varying the delay time within the p-bit circuit, they controlled the effective temperature of the probabilistic bits, successfully converging to the ground state and demonstrating the computation of an optimal combination. This highlights the design’s ability to perform computations without extensive parameter adjustments. The design utilizes stochastic magnetic tunnel junctions (MTJs) and digital circuits—specifically delay circuits—to achieve these functions. Crucially, the digital circuitry compensates for natural variations between devices, ensuring robustness despite manufacturing differences. This approach avoids bulky, power-hungry digital-to-analog converters (DACs) found in earlier designs, paving the way for scalable probabilistic computing hardware. Source: https://www.tohoku.ac.jp/en/press/fully_digital_design_paves_way_for_probabilistic_computing.html Tags: