Nysx: FPGA Accelerator Achieves Accurate, Energy-Efficient Hyperdimensional Graph Classification at the Edge
Summarize this article with:
Real-time and energy-efficient graph classification is crucial for a growing number of applications, and researchers are increasingly turning to brain-inspired computing methods to meet these demands. Jebacyril Arockiaraj, Dhruv Parikh, and Viktor Prasanna, all from the University of Southern California, present a novel approach utilising Hyperdimensional Computing and Nyström kernel approximations, implemented as a dedicated FPGA accelerator called NysX. This work addresses key challenges in edge deployment, including data redundancy, memory limitations, and computational bottlenecks, by integrating a hybrid landmark selection strategy, a streaming architecture, and a minimal-perfect-hash lookup engine. The resulting NysX system achieves significant speedup and energy efficiency gains over conventional CPU and GPU implementations, while simultaneously improving classification accuracy on standard graph classification benchmarks, representing a substantial advance for deploying complex graph analytics on resource-constrained edge devices. This work addresses key challenges in edge deployment, including data redundancy, memory limitations, and computational bottlenecks, by integrating a hybrid landmark selection strategy, a streaming architecture, and a minimal-perfect-hash lookup engine. The resulting NysX system achieves significant speedup and energy efficiency gains over conventional CPU and GPU implementations, while simultaneously improving classification accuracy on standard graph classification benchmarks, representing a substantial advance for deploying complex graph analytics on resource-constrained edge devices.,.
Scientists Method Scientists developed NysX, a novel end-to-end FPGA accelerator designed to perform Nyström-based Hyperdimensional Computing (HDC) for graph classification on edge devices, addressing limitations in both accuracy and efficiency. The study pioneers a method for real-time, energy-efficient inference by tackling challenges related to landmark sample redundancy, on-chip memory constraints, codebook lookup times, and load imbalance during sparse matrix-vector multiplication. Researchers implemented a hybrid landmark selection strategy, combining uniform sampling with determinantal point processes (DPPs) to reduce redundancy while simultaneously improving classification accuracy. To overcome limitations in storing the Nyström projection matrix, the team engineered a streaming architecture that maximizes external memory bandwidth utilization, enabling the processing of large datasets without being constrained by on-chip memory capacity. A minimal-perfect-hash lookup engine was developed to provide O(1) key-to-index mapping with minimal on-chip memory overhead, significantly reducing the time required for codebook lookups and accelerating the overall inference process. Furthermore, scientists designed sparsity-aware SpMV engines with static load balancing, ensuring efficient utilization of computational resources and minimizing performance bottlenecks caused by irregular data sparsity. Implemented on an AMD Zynq UltraScale+ FPGA, NysX demonstrated a 6. 85× speedup and 169× energy efficiency gain over optimized CPU baselines, and a 4. 32× speedup and 314× energy efficiency gain over optimized GPU baselines. Importantly, the study achieved a 3. 4% average improvement in classification accuracy across TUDataset benchmarks, demonstrating the effectiveness of the proposed optimizations.,. NysX Accelerates Graph Classification on FPGAs Scientists achieved a significant breakthrough in energy-efficient graph classification by developing NysX, a novel FPGA accelerator for Nyström-based Hyperdimensional Computing (HDC). This work addresses the challenges of deploying complex graph algorithms on resource-constrained edge devices, delivering real-time inference with substantial improvements in both speed and energy consumption.
The team implemented a hybrid landmark selection strategy, combining uniform sampling with determinantal point processes, which reduced redundancy in landmark samples while simultaneously improving classification accuracy. Experiments demonstrate an average accuracy improvement of 3. 4% across standard TUDataset benchmarks. The core of NysX lies in a streaming architecture designed to maximize external memory bandwidth utilization, issuing contiguous reads that match the memory interface width and overlapping fetch and compute operations via a FIFO. This approach, guided by roofline analysis, significantly enhances data throughput and minimizes processing bottlenecks. Furthermore, the team designed a minimal-perfect-hash engine that maps computed codes to histogram indices in constant time, enabling parallel histogram updates with negligible on-chip memory overhead. Measurements confirm this engine achieves O(1) time complexity for key-to-index mapping. To address irregular sparsity in the propagation kernel evaluation, scientists developed specialized Sparse Matrix-Vector (SpMV) processing elements. These PEs reduce memory footprint and energy consumption by exploiting the sparsity in both adjacency and landmark histogram matrices. A static load-balancing mechanism partitions rows across processing elements, mitigating the impact of irregular sparsity and ensuring efficient utilization of compute resources. Comprehensive testing on the AMD Zynq FPGA demonstrates NysX achieves 6. 85× speedup and 169× energy efficiency over optimized CPU baselines, and 4. 32× speedup and 314× energy efficiency over GPU baselines. These results represent a substantial advancement in the field of edge computing and pave the way for deploying sophisticated graph algorithms on low-power devices.,. NysX Accelerates Graph Classification on FPGAs This work presents NysX, a novel field-programmable gate array (FPGA) accelerator designed for Nyström-based hyperdimensional computing (HDC) applied to graph classification.
The team successfully integrated four key optimizations to address challenges in edge computing, including a hybrid landmark selection strategy, a streaming architecture for efficient memory use, a minimal-perfect-hash lookup engine, and statically load-balanced sparse matrix vector multiplication. These innovations enable real-time, energy-efficient inference on resource-constrained platforms, demonstrably improving both speed and accuracy compared to existing methods. Implemented on a Zynq UltraScale+ FPGA, NysX achieves up to 6. 👉 More information 🗞 NysX: An Accurate and Energy-Efficient FPGA Accelerator for Hyperdimensional Graph Classification at the Edge 🧠 ArXiv: https://arxiv.org/abs/2512.08089 Tags: