Universal Logical Operations Implemented in Silicon Donor Quantum Processor
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Universal Logical Operations Implemented in Silicon Donor Quantum Processor Researchers from the Shenzhen International Quantum Academy have demonstrated a silicon-based quantum processor capable of executing a universal set of logical gate operations. The device utilizes a cluster of five phosphorus donor nuclear spins embedded in an isotopically purified silicon-28 lattice, patterned with atomic precision via scanning tunneling microscopy (STM) lithography. To manage environmental noise, the system implements the [[4, 2, 2]] quantum error-detecting code, which encodes two logical qubits using four physical qubits. This architecture represents the first instance of universal logical operations being characterized within a silicon spin platform, which is traditionally valued for its compatibility with standard semiconductor manufacturing processes. The technical implementation included the characterization of a universal logical gate set, comprising single-qubit Clifford gates, a simultaneous Hadamard gate, and a two-qubit CNOT gate. The non-Clifford T gate was achieved using the gate-by-measurement method, which involves an ancillary nuclear spin to inject the required phase rotation. Experimental results showed average physical gate fidelities exceeding 95%, while the logical coherence times were measured at approximately 208 microseconds. The system exhibited a strong noise bias, with phase-flip (Z) errors significantly dominating bit-flip (X) errors—a characteristic that may reduce the hardware overhead required for larger-scale fault-tolerant architectures. The processor’s utility was evaluated through a Variational Quantum Eigensolver (VQE) algorithm to compute the ground-state energy of the water molecule (H2O). By applying three error mitigation techniques—parity checks, Clifford fitting, and symmetry verification—the researchers reported an average energy deviation of 22.7 mHa from theoretical values. This demonstration confirms the feasibility of running practical quantum algorithms on logical silicon qubits. The next stages of development focus on reducing cross-talk between donor clusters and scaling the architecture into larger arrays to accommodate more complex error-correction schemes. For the complete technical results and data on the silicon logical processor, consult the Nature Nanotechnology study here, the report from the South China Morning Post here, and the technical summary at Interesting Engineering here. March 28, 2026 Mohamed Abdel-Kareem2026-03-28T10:33:53-07:00 Leave A Comment Cancel replyComment Type in the text displayed above Δ This site uses Akismet to reduce spam. Learn how your comment data is processed.