Trying to understand the value of cryoCMOS over room temperature control
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My background - condensed matter physics (superconductivity), but fairly new to Quantum computing architectures, and looking to learn. my understanding of cryoCMOS is that the advantage is we need way less room temp -> cryostat cabling to control the # of required qubits. okay fine, but here's what i don't understand: - cryoCMOS is supposed to sit on the 4K stage. doesn't that mean we have just as much 4K -> mK stage cabling as before? Are the cryoCMOS folks saying that the thermal bottleneck really was room temp -> 4K cabling, and not 4K -> mK cabling? - has any group simulated/calculated/measured that CMOS dissipation on the 4K stage is lower heat load than the required wiring to room temp? - a bit of devil's advocate: what's so bad about room temp control? It scales as O(n) where n is the required number of qubits. If the goal is to beat classical performance on problems that scale as O(exp(n)), then... don't we just win by more engineering? Going from 100 -> 1000 qubits? just use 10x the # of pules tubes. It does not seem like cryoCMOS changes the O(n) analysis at all. In the meantime the classical guys have to make their classical computer exponentially larger. As long as the solution stays O(n), does it actually matter whichtechnology enables us getting there? To some extent, same questions for the people using RSFQ technology e.g. McDermott at Wisconsin. feels like a lot more work to try to get that running than dedicated FPGA room temp circuits and good superconducting ribbon cables. Feel free to hit me with your best intro papers/textbooks if the answer is in a well-known text. thank you! submitted by /u/Substantial-Duck9458 [link] [comments]