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SEALSQ targets CMOS-compatible architectures for scalable quantum systems - eeNews Europe

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⚡ Quantum Brief
Geneva-based SEALSQ is prioritizing CMOS-compatible quantum architectures to accelerate industrial-scale deployment, focusing on silicon spin qubits and electrons-on-helium platforms that leverage existing semiconductor fabrication techniques. The company argues silicon-based approaches—unlike superconducting or ion-trap systems—align with mainstream CMOS processes, enabling higher yields, scalability, and co-integration of quantum and classical control circuitry using technologies like FDSOI. CEO Carlos Moreira claims this semiconductor alignment provides a competitive edge by reducing custom fabrication barriers, speeding lab-to-production transitions, and embedding security-by-design principles into quantum hardware development. SEALSQ is integrating post-quantum cryptography (PQC) and secure elements into quantum control systems to protect firmware, calibration data, and cloud communications, addressing vulnerabilities as quantum computers threaten classical encryption. The strategy positions SEALSQ to bridge quantum research and real-world applications, targeting government and critical infrastructure markets where scalable, secure quantum systems are essential for future deployment.
SEALSQ targets CMOS-compatible architectures for scalable quantum systems - eeNews Europe

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SEALSQ targets CMOS-compatible architectures for scalable quantum systems News | March 2, 2026 By Asma Adhimi SEALSQ is doubling down on semiconductor-aligned quantum computing, sharpening its focus on CMOS-compatible architectures as it looks to bridge the gap between quantum research and industrial-scale deployment. The Geneva-based company says the move reflects a belief that silicon-friendly approaches offer the most realistic path to scalable quantum systems. For eeNews Europe readers, the announcement matters because it connects quantum computing with familiar semiconductor manufacturing flows. It also highlights how security and post-quantum cryptography are becoming core design elements, not add-ons, as quantum hardware inches closer to real-world use. Silicon-based paths to scale SEALSQ Corp (NASDAQ: LAES) announced it is prioritizing silicon spin qubits and electrons-on-helium platforms, two approaches that can leverage established CMOS fabrication and integration techniques. Silicon spin qubits rely on electrons confined in silicon structures that can be produced using processes similar to mainstream CMOS, offering potential advantages in yield and scalability. Electrons-on-helium qubits, meanwhile, place electrons above superfluid helium on a silicon substrate and use CMOS-compatible electronics for control, offering a low-noise alternative. According to SEALSQ, CMOS compatibility is not just about manufacturing efficiency. Quantum processors require dense control wiring, high-speed signal routing, cryogenic electronics, and continuous calibration. Silicon-based platforms make it possible to co-design and eventually co-integrate quantum devices with classical CMOS control circuitry. The company points to fully depleted silicon-on-insulator (FDSOI) as a promising compromise technology, balancing low noise and power consumption at the wafer level. A semiconductor advantage over rivals Founder and CEO Carlos Moreira argues that this alignment gives SEALSQ an edge over other quantum approaches. “From our perspective, this technology alignment is a real advantage over other quantum approaches, such as superconducting or ion-trap systems. While those platforms are scientifically impressive, they often depend on specialized materials, custom fabrication steps, or complex optical and vacuum setups that do not align as naturally with mainstream semiconductor manufacturing,” he said. He added that silicon-based approaches are “designed from the start to evolve within the semiconductor ecosystem,” enabling faster learning cycles and a smoother transition from lab to production. Crucially, Moreira also emphasized security-by-design, noting that the strategy allows SEALSQ to embed post-quantum cryptography and hardware-based trust directly into quantum systems. Security built into quantum systems Alongside its hardware roadmap, SEALSQ is integrating post-quantum cryptography (PQC) and secure elements into quantum control architectures. As quantum computers threaten classical public-key cryptography, the company sees PQC as essential for protecting firmware updates, calibration data, FPGA configurations, and communications between control electronics and cloud orchestration layers. By fabricating secure elements alongside quantum control circuitry, SEALSQ aims to enable trusted boot, device attestation, and secure key storage. Moreover, the company believes this will be critical as quantum computers evolve from isolated lab tools into networked, mission-critical infrastructure. SEALSQ’s message is clear: scalable quantum computing will only succeed if it aligns with semiconductor manufacturing realities and is secure enough for deployment in government, industrial, and critical infrastructure environments. If you enjoyed this article, you will like the following ones: don't miss them by subscribing to : eeNews on Google News Share: Linked Articles SEALSQ targets CMOS-compatible architectures for scalable quantum systems March 2, 2026 US outlines AI sovereignty initiative at India AI Impact Summit March 2, 2026 Nokia validates quantum-safe network blueprint for Canada February 27, 2026 Nokia and AWS push agentic AI network slicing into live 5G February 27, 2026 AMD and Meta deepen AI partnership with 6GW GPU roadmap February 26, 2026 Related Articles Industrial eMMC targets long-term supply for embedded designs

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Source: Google News – Quantum Computing