Rigetti Advances QPU Performance by Implementing CZ Gates in Cepheus-1–36Q
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Rigetti Computing has enhanced the performance of its quantum processing units by implementing CZ gates within its newest QPU, Cepheus-1, 36Q. The company transitioned from iSWAP-type entangling gates, initially used on Ankaa-class processors, to the controlled-phase CZ gate. This move is designed to improve compilation efficiency and scalability for quantum algorithms, particularly those crucial for quantum error correction. This shift allows for more streamlined parity-check circuits, a key component in detecting and correcting errors in quantum computations. “CZ is also an entangling two-qubit gate, and together with single-qubit operations it is fully universal,” explains Stefano Poletto, Director, Quantum Engineering, adding that the gate’s design fits well with important algorithmic patterns. Like iSWAP, three √ iSWAP gates with one-qubit rotations can generate the full space of two-qubit unitaries. Rigetti has demonstrated the new gate achieves speeds under 30 nanoseconds with fidelity exceeding 99.9% on prototype devices. iSWAP Gates for Expressivity in Ankaa-Class Processors Rigetti Computing’s evolution in quantum processing unit design initially favored iSWAP-type entangling gates for their ability to efficiently represent complex quantum operations, a characteristic described as strong expressivity in NISQ circuits. This strategic choice stemmed from the need for versatile gates during the Noisy Intermediate-Scale Quantum (NISQ) era, where maximizing computational potential with limited resources was paramount. Rigetti’s fourth-generation Ankaa-class QPUs were initially introduced with iSWAP and √ iSWAP as native entangling gates. Unlike some gate types, iSWAP, alongside its √ iSWAP variant, could generate the full spectrum of two-qubit operations with a relatively small number of applications; “Like iSWAP, three √ iSWAP gates with one-qubit rotations are able to generate the full space of two-qubit unitaries.” This inherent efficiency translated to faster computation and reduced overhead in early quantum algorithms. The appeal of √ iSWAP specifically lay in its speed advantage; the gate is typically twice as fast as the iSWAP due to the smaller rotation angle. However, real-world implementations weren’t always perfect.
The team acknowledged that hardware imperfections could introduce a slight deviation from a true iSWAP, resulting in a small conditional phase. Despite this, Rigetti engineers found this deviation tolerable, noting that for small phases, the set of representable two-qubit unitaries remains large. This tolerance was a key factor in maintaining the iSWAP’s position as a native gate on earlier Ankaa-class processors, allowing for a balance between ideal performance and practical implementation. The shift toward CZ gates in the latest Cepheus processors, however, signals a move toward prioritizing scalability and error correction. While iSWAP excelled in expressivity, the CZ gate offers advantages in circuits designed for parity checks, a crucial component of many quantum error correction schemes. Implementing parity encoding with CZ gates requires fewer gates than with iSWAP; each CNOT can be implemented with one CZ gate (plus single-qubit rotations), or two iSWAP gates (plus single-qubit rotations). Beyond algorithmic efficiency, the transition to CZ addresses a significant limitation of iSWAP gates within the control system. iSWAP necessitates information sharing between processors during runtime, imposing a quadratic cost in both time and memory. “For programs with dynamic control flow, this sharing must occur at runtime,” explained Stefano Poletto, Director of Quantum Engineering. CZ gates circumvent this issue, removing the scaling limitation and paving the way for larger, more complex quantum computations, particularly those leveraging surface-code-style error correction protocols. Cepheus-1, 36Q Transition to CZ Gates for Parity Checks The pursuit of stable, scalable quantum computation increasingly focuses on the foundational gates that underpin algorithms. While early superconducting quantum processing units (QPUs) often relied on iSWAP gates for their flexibility, Rigetti Computing’s latest Cepheus-1, 36Q processor represents a deliberate shift toward controlled-phase, or CZ, gates. This transition isn’t merely about achieving higher two-qubit fidelity, but fundamentally alters how quantum programs are compiled, calibrated, and ultimately, scaled toward practical error correction. The core rationale behind embracing CZ gates lies in their suitability for parity-check circuits, essential components of quantum error correction. Consequently, “CZ is often the more direct and efficient choice for circuits dominated by parity-check structure.” This efficiency extends beyond algorithmic convenience; iSWAP gates, requiring information sharing between processors during runtime to transfer phase information, impose limitations on program complexity. Beyond scalability, the implementation of CZ gates on Cepheus-1, 36Q leverages an adiabatic approach, modulating the tunable coupler while maintaining qubits at their optimal operating frequencies. This contrasts with resonant CZ implementations that require detuning qubits, potentially reducing coherence. Rigetti’s adiabatic CZ relies on dynamical phase accumulation arising from level repulsion and hybridization in the two-excitation manifold, achieved by carefully tuning the coupler frequency. This method offers several advantages, including a simplified control scheme, driven by a single coupler-flux waveform, and increased robustness to fabrication variations. Stefano Poletto highlights that the adiabatic CZ is attractive not only because it performs well, but because it is simple and scalable. To our knowledge, this result places our implementation among the fastest reported adiabatic CZ gates for transmon-based superconducting qubits, based on publicly available literature. Adiabatic CZ Implementation via Tunable Coupler Modulation Rigetti Computing is refining its approach to quantum gate implementation, shifting to a proprietary adiabatic CZ entangling gate. This change is intended to improve fidelity for both QPUs and quantum error correction.
The team has designed the gate to be simple and scalable. Stefano Poletto explains that the adiabatic CZ is attractive not only because it performs well, but because it is simple and scalable. One control knob drives the gate, using a single coupler-flux waveform. Qubits stay at their sweet spots during the entangling operation, requiring no qubit frequency excursion. Implementing parity encoding with CZ gates requires fewer gates than with iSWAP; each CNOT can be implemented with one CZ gate (plus single-qubit rotations), or two iSWAP gates (plus single-qubit rotations). Additionally, phase-swap gates, like iSWAP, necessitate information sharing across processors during runtime, imposing a quadratic cost in both time and memory.
The team highlights that the adiabatic CZ is attractive not only because it performs well, but because it is simple and scalable, according to Stefano Poletto. One control knob: the gate is driven by a single coupler-flux waveform. Qubits stay at their sweet spots: no qubit frequency excursion is required during the entangling operation. Source: https://medium.com/rigetti/rigettis-new-proprietary-adiabatic-cz-entangling-gate-for-high-fidelity-qpus-and-quantum-error-f56fe3caadce Tags: