memQ Launches Extensible Distributed Quantum Compiler (xDQC) via NVIDIA CUDA-Q
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memQ Launches Extensible Distributed Quantum Compiler (xDQC) via NVIDIA CUDA-Q memQ has announced the roadmap for its Extensible Distributed Quantum Compiler (xDQC), a software framework built on the NVIDIA CUDA-Q platform designed for modular, networked quantum processing units (QPUs). This orchestration layer transitions quantum computing from monolithic architectures to distributed clusters by treating QPU-to-QPU links as first-class components within the quantum circuit. The xDQC intelligently routes and partitions workloads across multiple nodes based on qubit modality, hardware availability, and specific network topologies, such as All-to-All, Grid, Ring, and Hub configurations. The framework utilizes hardware-aware noise models to generate a “digital twin” of distributed quantum processors, enabling the co-design of hardware and architecture before physical deployment. By integrating NVIDIA’s GPU-accelerated tensornet-MPS (Matrix Product State) and statevector simulation backends, xDQC can validate large-scale partitioned circuits that exceed the capacity of standard CPU-based simulators. Benchmarks include a 192-qubit GHZ circuit and a 30-qubit Quantum Volume (QV) circuit, where the compiler reduced e-bit (entangled pair) consumption in sparse topologies by dynamically placing highly interacting qubits on adjacent or directly connected nodes. Technically, the xDQC functions by dividing circuits into sequential layers and constructing interaction graphs to minimize expensive remote operations, such as gate teleportation and noisy swap operations. It supports heterogeneous architectures, allowing the integration of different qubit modalities and hardware from multiple vendors within a single network. The simulation pipeline uses Monte-Carlo noisy trajectory sampling to map local and remote operation errors to circuit-level performance, specifically evaluating Hellinger Fidelity against dark count noise probability in quantum links. The xDQC is designed to complement memQ’s xQNA hardware portfolio, which includes chip-scale Quantum Network Interface Controllers (QNICs), Quantum Memory Modules (QMMs), and Quantum Control Systems (QCS). Future development phases will incorporate a quantum network orchestration layer leveraging NVIDIA NVQLink to facilitate low-latency, dynamic scheduling of cross-QPU operations. This integration aims to bridge connections between QPUs and classical HPC environments, supporting the execution of quantum workloads at a scale required for future supercomputing applications. A preview of the xDQC is scheduled for the first half of 2026, with a full open-source release expected in June 2026. This open-ecosystem approach is intended to facilitate community-driven innovation in the “quantum internet” subsector, which is projected to reach a $15 billion market value by 2035. By providing an extensible platform for distributed compilation and simulation, memQ aims to establish standardized benchmarks for utility-scale, error-corrected quantum networks across metropolitan and wide-area infrastructures. For further technical details on the xDQC architecture and CUDA-Q simulation pipeline, consult the official memQ announcement here and the technical blog here. March 16, 2026 Mohamed Abdel-Kareem2026-03-16T18:56:47-07:00 Leave A Comment Cancel replyComment Type in the text displayed above Δ This site uses Akismet to reduce spam. Learn how your comment data is processed.