Gate structuring on n-type bilayer MoS₂ field-effect transistors for ultrahigh current density

Nature Materials (2026)Cite this article The foundry industry and academia are confronting the limits of Moore’s Law scaling for logic transistors. Silicon field‑effect transistors (FETs) now rely on gate‑all‑around structures and ultrathin channels, even at the cost of decreased carrier mobility and complex fabrication processes. Two‑dimensional (2D) semiconductors offer a promising alternative because they retain their crystalline quality at atomic thicknesses. Nonetheless, whether they truly exhibit higher performance than silicon remains questionable. Here, by implementing a dual‑gate structure on bilayer MoS2 FETs, we mitigate the fringing‑field barrier created by the elevated top contact and achieve high carrier densities without increasing fabrication complexity. Simulations and statistical analysis confirm that the dual‑gate compensates the fringe field, enabling a drain current of 1.55 mA µm−1 even with conventional gold contacts. Quantum‑transport simulation indicates that, with further gate‑length and equivalent‑oxide‑thickness scaling, the on-state current can reach levels comparable to silicon FETs at the 3-nm node, and monolithic 3D integration can extend the applicability of dual‑gate 2D transistors to future logic technologies.This is a preview of subscription content, access via your institution Access Nature and 54 other Nature Portfolio journals Get Nature+, our best-value online-access subscription $32.99 / 30 days cancel any timeSubscribe to this journal Receive 12 print issues and online access $259.00 per yearonly $21.58 per issueBuy this articleUSD 39.95Prices may be subject to local taxes which are calculated during checkout Source data are provided with this paper. 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Sci. 463, 758–766 (2019).Article CAS Google Scholar International Technology Roadmap for Semiconductors (ITRS) 2007 Edition. https://www.semiconductors.org/resources/2007-international-technology-roadmap-for-semiconductors-itrs/, (Semiconductor Industry Association, 2007).Download referencesThis work was supported by Samsung Advanced Institute of Technology, Samsung Electronics Co., Ltd.These authors contributed equally: Junyoung Kwon, Kyoung Yeon Kim, Dongwon Jang.Samsung Advanced Institute of Technology, Samsung Electronics Co., Ltd, Suwon, Republic of KoreaJunyoung Kwon, Min Seok Yoo, Alum Jung, Dong-Su Ko, Yoonhoo Ha, Huije Ryu, Yeonchoo Cho, Changhyun Kim, Eunji Yang, Eun Kyu Lee, Chang-Seok Lee, Sang Won Kim, Kyung-Eun Byun, Minsu Seol & Jeehwan KimComputational Science Engineering Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd, Giheung, Republic of KoreaKyoung Yeon Kim, Woon Ih Choi, Uihui Kwon & Dae Sin KimSchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USADongwon JangDepartment of Electrical and Computer Engineering, University of Southern California, Los Angeles, CA, USASung Kyu LimDepartment of Mechanical Engineering, and Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA, USAJeehwan KimSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarSearch author on:PubMed Google ScholarJ. Kwon, K.Y.K., D.J., K.-E.B., M.S. and J. Kim conceived the project and defined the research strategy. J. Kwon designed, fabricated and measured all wafer‑scale devices, performed the data analysis and drafted the paper. K.Y.K. carried out all TCAD/NEGF simulations, developed the device‑level models, supervised the simulation work and contributed to paper preparation. D.J. interpreted the simulation results, helped shape the logical flow of the paper and participated in writing. M.S.Y. and A.J. were responsible for the wafer‑scale growth of monolayer and bilayer MoS2 films by MOCVD. D.-S.K. performed TEM imaging and analysis. Y.H. performed quantum‑capacitance simulations. H.R. participated in the fabrication of low‑k spacer devices. W.I.C. carried out DFT‑based calculations of the MoS2 electronic structure. Y.C. led the discussion on MoS2 transport mechanisms. C.K. contributed to the discussion of the experimental results. E.Y. acquired the SEM images and assisted with structural characterization. E.K.L. analysed the electrical‑measurement data and led the discussion of these results. C‑S.L. and S.W.K. provided the overall direction of the research, gave technical guidance and reviewed the paper. U.K. and D.S.K. discussed the simulation strategy, guided its development and supervised K.Y.K. S.K.L. supervised D.J. and led the discussion on future logic technologies. K.‑E.B., M.S. and J. Kim supervised J. Kwon, contributed to the interpretation of the results and co‑wrote the paper. All authors discussed the results, contributed to the interpretation of the data and approved the final version of the paper.Correspondence to Kyoung Yeon Kim, Sung Kyu Lim, Kyung-Eun Byun, Minsu Seol or Jeehwan Kim.The authors declare no competing interests.Nature Materials thanks Wenzhong Bao, Lain-Jong Li and Yanqing Wu for their contribution to the peer review of this work.Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.a,b, Transfer curves of single gate (green) and dual gate (navy) monolayer MoS2 FETs plotted on both semi-log (a) and linear (b) scales. c,d, Transfer curves of single gate (orange) and dual gate (wine) bilayer MoS2 FETs plotted on both semi-log (c) and linear (d) scales.Source dataa, Image mapping the ratio of A peak intensity (IA) of monolayer MoS2 to Si peak intensity (ISi). b, Image mapping the distance between the E peak position (PE) and A peak position (PA) of monolayer MoS2. c, Image mapping the ratio of IA of bilayer MoS2 to ISi. d, Image mapping the distance between the PE and PA of bilayer MoS2. Only the 100 mm×100 mm region is mapped, as the device fabrication area was confined to the 100 mm centre region of the wafer.Source dataa, Transfer curves (σsh – Vgs) of back gate (red), top gate (blue), and dual gate (green) MoS2 FETs fabricated across the entire 200-mm wafer. b,c, Statistical distribution of Ion and subthreshold swing (SS) for back gate (red), top gate (blue), and dual gate (green) configurations. In dual gate configurations, not only Ion and SS have substantially improved, but the variance has also been greatly reduced. Here, the numbers of measured back‑gate, top‑gate, and dual‑gate FETs are 40, 42, and 48, respectively. The box represents the 25 %–75 % range, the line in the middle indicates the median, and the circle denotes the mean value. d, Statistical analysis of field-effect (FE) mobility of dual-gate FETs as a function of Lch. The consistent FE mobility values across different Lch values indicate that the RC has sufficiently decreased. e, Threshold voltage (Vth) of dual-gate FETs extracted using the linear extrapolation method (hollow hexagon) from the transfer curve and the Vth extracted using the constant current method (filled hexagon). The constant current value used was 50 nA. The number of devices for d and e by Lch are: 115 devices for 500 nm, 60 for 1 µm, 34 for 2 µm, 35 for 5 µm, 36 for 10 µm, and 35 for 20 µm. Data in d, e are presented as mean values +/- standard deviation. f. A wafer map showing die-by-die device yield for the dual gate structure, demonstrating a high yield of 99.7%.Source dataa, Schematics showing SiO2 spacer fabrication process. Source drain electrodes were fabricated by patterning a photoresist with a large undercut, followed by Au evaporation, subsequent SiO2 evaporation, and a single lift off step, resulting in a SiO2 spacer that covers the Au contacts. b, Comparison of the structure near the original contact (top) and the modified structure with an SiO2 spacer (bottom). Because the dielectric constant of SiO2 is lower than that of HfOx, the fringing capacitance associated with the SiO2 spacer (Cf, SiO2) is smaller than the fringing capacitance that arises from the HfOx filled field (Cf, HfOx). c, Cross sectional TEM image of a fabricated MoS2 FET that incorporates the SiO2 spacer. d,e, Transfer curves of the reference structure without a spacer: back gate configuration (d) and dual gate configuration (e). f,g, Transfer curves of the FETs with a SiO2 spacer: back gate configuration (f) and dual gate configuration (g). Insertion of the spacer reduces the fringing field, resulting in higher current and improved variation. h, Comparison of Ion at Vgs = 3 V extracted from the preceding transfer curves. After SiO2 spacer insertion, both the back‑gate and dual‑gate configurations exhibit a pronounced increase in Ion. All data in this figure are presented as mean values +/- standard deviation.Source dataa, Total resistance (Rtot) as a function of channel length (Lch) for single gate and monolayer MoS2 FET at a planar carrier density (n2D) of 7.69 ×1012 cm−2. The number of devices for each Lch is as follows: 10 devices for 30 nm, 52 for 40 nm, 67 for 50 nm, 16 each for 60, 70, 80, 150, 200, 250, and 300 nm, and 15 for 100 nm. b, Same plot for dual gate and monolayer MoS2 FET at n2D of 1.51 ×1013 cm−2. 13 devices for 30 nm, 69 for 40 nm, 85 for 50 nm, and 18 each for 60, 70, 80, 100, 150, 200, 250, and 300 nm. c, Same plot for single gate and bilayer MoS2 FET at n2D of 1.04 ×1013 cm−2. 5 devices for 30 nm, 32 for 40 nm, 55 for 50 nm, 14 for 60 nm, 15 for 70 nm, 14 for 80 nm, 14 for 100 nm, 16 for 150 nm, 16 for 200 nm, 16 for 250 nm, and 17 for 300 nm. d, Same plot for dual gate and bilayer MoS2 FET at n2D of 1.7 ×1013 cm−2. 13 devices for 30 nm, 57 for 40 nm, 78 for 50 nm, 16 for 60 nm, 15 for 70 nm, 16 for 80 nm, 17 for 100 nm, 17 for 150 nm, 17 for 200 nm, 18 for 250 nm, and 17 for 300 nm. All data in this figure are presented as mean values +/- standard deviation.Source dataa, NEGF simulation models of bilayer MoS2 dual-gate FETs with Lg = 30 nm, 12 nm, and 5 nm, from top to bottom. The bilayer MoS2 was modelled with a vdW gap between the two MoS2 layers. b, Transfer curves at Vds = 0.7 V for Lg = 30 nm (pink), 12 nm (purple), and 5 nm (navy blue) calculated by quantum simulation. As Lg decreases to 5 nm, the transfer curve (navy blue) becomes increasingly similar to the ballistic transport-assumed transfer curve (light blue), indicating a higher proportion of ballistic transport under shorter Lg.Source dataa, NEGF simulation models of Si GAAFETs with Lg = 12 nm and 5 nm, from top to bottom. The thickness of the Si channel is fixed to 4 nm. b, Transfer curves at Vds = 0.7 V for 12 nm (pink), and 5 nm (orange) calculated by quantum simulation. Unlike MoS2, Si exhibits a notable degradation in SS due to the short-channel effect as Lg is reduced to 5 nm.Source dataSupplementary Figs. 1–20.Raw data used in the plot.Raw data used in the plot.Raw data used in the plot.Raw data used in the plot.Raw data used in the plot.Raw data used in the plot.Raw data used in the plot.Raw data used in the plot.Raw data used in the plot.Raw data used in the plot.Raw data used in the plot.Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.Reprints and permissionsKwon, J., Kim, K.Y., Jang, D. et al. Gate structuring on n-type bilayer MoS2 field-effect transistors for ultrahigh current density. Nat. Mater. (2026). https://doi.org/10.1038/s41563-025-02452-yDownload citationReceived: 24 June 2024Accepted: 18 November 2025Published: 09 January 2026Version of record: 09 January 2026DOI: https://doi.org/10.1038/s41563-025-02452-yAnyone you share the following link with will be able to read this content:Sorry, a shareable link is not currently available for this article. Provided by the Springer Nature SharedIt content-sharing initiative