Diversity Methods for Improving Convergence and Accuracy of Quantum Error Correction Decoders Through Hardware Emulation
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AbstractAs quantum computing moves toward fault-tolerant architectures, quantum error correction (QEC) decoder performance is increasingly critical for scalability. Understanding the impact of transitioning from floating-point software to finite-precision hardware is essential, as hardware decoder performance affects code distance, qubit requirements, and connectivity between quantum and classical control units. This paper introduces a hardware emulator to evaluate QEC decoders using real hardware instead of software models. The emulator can explore $10^{13}$ different error patterns in 20 days with a single FPGA device running at 150 MHz, guaranteeing the decoder's performance at logical rates of $10^{-12}$, the requirement for most quantum algorithms. In contrast, an optimized C++ software on an Intel Core i9 with 128 GB RAM would take over a year to achieve similar results. The emulator also enables the storage of uncorrectable error patterns that generate logical errors, allowing for offline analysis and the design of new decoders. Using results from the emulator, we propose a method that combines several belief propagation (BP) decoders with different quantization levels, which we define as a diversity-based decoder. Individually, these decoders may show subpar error correction, but together they outperform the floating-point version of BP for quantum low-density parity-check (QLDPC) codes like hypergraph or lifted product. Preliminary results with circuit-level noise and bivariate bicycle codes suggest that hardware insights can also improve software. Our diversity-based proposal achieves a similar logical error rate as the well-known approach, BP with ordered statistics (BP+OSD) decoding, with average speed improvements ranging from 30% to 80%, and 10% to 120% in worst-case scenarios, while reducing post-processing algorithm activation from 47% to 96.93%, maintaining the same accuracy.► BibTeX data@article{GarciaHerrero2026diversitymethods, doi = {10.22331/q-2026-04-16-2071}, url = {https://doi.org/10.22331/q-2026-04-16-2071}, title = {Diversity {M}ethods for {I}mproving {C}onvergence and {A}ccuracy of {Q}uantum {E}rror {C}orrection {D}ecoders {T}hrough {H}ardware {E}mulation}, author = {Garcia-Herrero, Francisco and Valls, Javier and Vergara-Picazo, Llanos and Torres, Vicente}, journal = {{Quantum}}, issn = {2521-327X}, publisher = {{Verein zur F{\"{o}}rderung des Open Access Publizierens in den Quantenwissenschaften}}, volume = {10}, pages = {2071}, month = apr, year = {2026} }► References [1] 4 Z. Babar, P. Botsinis, D. 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AbstractAs quantum computing moves toward fault-tolerant architectures, quantum error correction (QEC) decoder performance is increasingly critical for scalability. Understanding the impact of transitioning from floating-point software to finite-precision hardware is essential, as hardware decoder performance affects code distance, qubit requirements, and connectivity between quantum and classical control units. This paper introduces a hardware emulator to evaluate QEC decoders using real hardware instead of software models. The emulator can explore $10^{13}$ different error patterns in 20 days with a single FPGA device running at 150 MHz, guaranteeing the decoder's performance at logical rates of $10^{-12}$, the requirement for most quantum algorithms. In contrast, an optimized C++ software on an Intel Core i9 with 128 GB RAM would take over a year to achieve similar results. The emulator also enables the storage of uncorrectable error patterns that generate logical errors, allowing for offline analysis and the design of new decoders. Using results from the emulator, we propose a method that combines several belief propagation (BP) decoders with different quantization levels, which we define as a diversity-based decoder. Individually, these decoders may show subpar error correction, but together they outperform the floating-point version of BP for quantum low-density parity-check (QLDPC) codes like hypergraph or lifted product. Preliminary results with circuit-level noise and bivariate bicycle codes suggest that hardware insights can also improve software. Our diversity-based proposal achieves a similar logical error rate as the well-known approach, BP with ordered statistics (BP+OSD) decoding, with average speed improvements ranging from 30% to 80%, and 10% to 120% in worst-case scenarios, while reducing post-processing algorithm activation from 47% to 96.93%, maintaining the same accuracy.► BibTeX data@article{GarciaHerrero2026diversitymethods, doi = {10.22331/q-2026-04-16-2071}, url = {https://doi.org/10.22331/q-2026-04-16-2071}, title = {Diversity {M}ethods for {I}mproving {C}onvergence and {A}ccuracy of {Q}uantum {E}rror {C}orrection {D}ecoders {T}hrough {H}ardware {E}mulation}, author = {Garcia-Herrero, Francisco and Valls, Javier and Vergara-Picazo, Llanos and Torres, Vicente}, journal = {{Quantum}}, issn = {2521-327X}, publisher = {{Verein zur F{\"{o}}rderung des Open Access Publizierens in den Quantenwissenschaften}}, volume = {10}, pages = {2071}, month = apr, year = {2026} }► References [1] 4 Z. Babar, P. Botsinis, D. Alanis, S. X. Ng, and L. Hanzo, ``Fifteen years of quantum LDPC coding and improved decoding strategies,'' IEEE Access, vol. 3, pp. 2492–2519, Nov. 2015. [Online]. Available: https://doi.org/10.1109/ACCESS.2015.2503267 0pt. https://doi.org/10.1109/ACCESS.2015.2503267 [2] 4 J. Roffe, D. R. White, S. Burton, and E. Campbell, ``Decoding across the quantum low-density parity-check code landscape,'' Phys. Rev. Res., vol. 2, p. 043423, Dec 2020. [Online]. Available: https://doi.org/10.1103/PhysRevResearch.2.043423 0pt. https://doi.org/10.1103/PhysRevResearch.2.043423 [3] 4 P. Panteleev and G. Kalachev, ``Degenerate quantum LDPC codes with good finite length performance,'' Quantum, vol. 5, p. 585, July 2021. [Online]. Available: https://doi.org/10.22331/q-2021-11-22-585 0pt. https://doi.org/10.22331/q-2021-11-22-585 [4] 4 J. Valls, F. Garcia-Herrero, N. Raveendran, and B. Vasić, ``Syndrome-based min-sum vs OSD-0 decoders: FPGA implementation and analysis for quantum LDPC codes,'' IEEE Access, vol. 9, pp. 138 734–138 743, Sep. 2021. [Online]. Available: https://doi.org/10.1109/ACCESS.2021.3118544 0pt. https://doi.org/10.1109/ACCESS.2021.3118544 [5] 4 T. Müller, T. Alexander, M. E. Beverland, M. Bühler, B. R. Johnson, T. Maurer, and D. Vandeth, ``Improved belief propagation is sufficient for real-time decoding of quantum memory,'' preprint arXiv:2506.01779, 2025. [Online]. Available: https://doi.org/10.48550/arXiv.2506.01779 0pt. https://doi.org/10.48550/arXiv.2506.01779 arXiv:2506.01779 [6] 4 P. Fuentes, J. Etxezarreta Martinez, P. M. Crespo, and J. Garcia-Frías, ``Degeneracy and Its Impact on the Decoding of Sparse Quantum Codes,'' IEEE Access, vol. 9, pp. 89 093–89 119, 2021. [Online]. Available: https://doi.org/10.1109/ACCESS.2021.3089829 0pt. https://doi.org/10.1109/ACCESS.2021.3089829 [7] 4 N. Raveendran and B. Vasić, ``Trapping sets of quantum LDPC codes,'' Quantum, vol. 5, p. 562, July 2021. [Online]. Available: https://doi.org/10.22331/q-2021-10-14-562 0pt. https://doi.org/10.22331/q-2021-10-14-562 [8] 4 P.-J. H. Derks, A. Townsend-Teague, A. G. Burchards, and J. Eisert, ``Designing fault-tolerant circuits using detector error models,'' Quantum, vol. 9, p. 1905, Nov. 2025. [Online]. Available: https://doi.org/10.22331/q-2025-11-06-1905 0pt. https://doi.org/10.22331/q-2025-11-06-1905 [9] 4 C. Gidney, ``Stim: a fast stabilizer circuit simulator,'' Quantum, vol. 5, p. 497, Jul. 2021. [Online]. Available: https://doi.org/10.22331/q-2021-07-06-497 0pt. https://doi.org/10.22331/q-2021-07-06-497 [10] 4 H. Yao, W. A. Laban, C. Häger, A. G. i. Amat, and H. D. Pfister, ``Belief propagation decoding of quantum LDPC codes with guided decimation,'' in IEEE International Symposium on Information Theory, Athens, Greece, July 2024, pp. 2478–2483. [Online]. Available: https://doi.org/10.1109/ISIT57864.2024.10619083 0pt. https://doi.org/10.1109/ISIT57864.2024.10619083 [11] 4 A. Gong, S. Cammerer, and J. M. Renes, ``Toward Low-latency Iterative Decoding of QLDPC Codes Under Circuit-Level Noise,'' preprint arXiv:2403.18901, 2024. [Online]. Available: https://arxiv.org/abs/2403.18901 0pt. arXiv:2403.18901 [12] 4 J. Du Crest, M. Mhalla, and V. Savin, ``Stabilizer inactivation for message-passing decoding of quantum LDPC codes,'' in IEEE Information Theory Workshop, Mumbai, India, July 2022, pp. 488–493. [Online]. Available: https://doi.org/10.1109/ITW54588.2022.9965902 0pt. https://doi.org/10.1109/ITW54588.2022.9965902 [13] 4 J. du Crest, F. Garcia-Herrero, M. Mhalla, V. Savin, and J. Valls, ``Check-agnosia based post-processor for message-passing decoding of quantum LDPC codes,'' Quantum, vol. 8, p. 1334, May 2024. [Online]. Available: https://doi.org/10.22331/q-2024-05-02-1334 0pt. https://doi.org/10.22331/q-2024-05-02-1334 [14] 4 T. Hillmann, L. Berent, A. O. Quintavalle, J. Eisert, R. Wille, and J. Roffe, ``Localized statistics decoding for quantum low-density parity-check codes,'' Nature Communications, vol. 16, no. 1, Sep. 2025. [Online]. Available: http://dx.doi.org/10.1038/s41467-025-63214-7 0pt. https://doi.org/10.1038/s41467-025-63214-7 [15] 4 A. deMarti iOlius, I. E. Martinez, J. Roffe, and J. E. Martinez, ``An almost-linear time decoding algorithm for quantum LDPC codes under circuit-level noise,'' preprint arXiv:2409.01440, 2024. [Online]. Available: https://doi.org/10.48550/arXiv.2409.01440 0pt. https://doi.org/10.48550/arXiv.2409.01440 arXiv:2409.01440 [16] 4 S. Wolanski and B. Barber, ``Ambiguity Clustering: an accurate and efficient decoder for qLDPC codes,'' preprint arXiv:2406.14527, 2025. [Online]. Available: https://doi.org/10.48550/arXiv.2406.14527 0pt. https://doi.org/10.48550/arXiv.2406.14527 arXiv:2406.14527 [17] 4 J. Du Crest, F. Garcia-Herrero, M. Mhalla, V. Savin, and J. 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